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Si570/Si571
7. Ordering Information
The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and V DD . Specific device configurations are programmed into the Si570/Si571
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si570/Si571 XO/
VCXO series is supplied in an industry-standard, RoHS compliant, 8-pad, 5 x 7 mm package. Tape and reel
packaging is an ordering option.
57x
X
X
X
XXX XXX
D
G
R
R = Tape & Reel
Blank = Trays
570 Programmable
XO Product Family
571 Programmable
VCXO Product Family
1 st Option Code
Operating Temp Range (°C)
G –40 to +85 °C
Device Revision Letter
Six-Digit Start-up Frequency/I 2 C Address Designator
The Si57x supports a user-defined start-up frequency within the following
bands of frequencies: 10–945 MHz, 970–1134 MHz, and 1213–1417 MHz.
The start-up frequency must be in the same frequency range as that
specified by the Frequency Grade 3 rd option code.
A
B
C
D
E
F
G
V DD
3.3
3.3
3.3
3.3
2.5
2.5
2.5
Output Format Output Enable Polarity
LVPECL High
LVDS High
CMOS High
CML High
LVPECL High
LVDS High
CMOS High
The Si57x supports a user-defined I 2 C 7-bit address. Each unique start-up
frequency/I 2 C address combination is assigned a six-digit numerical code.
This code can be requested during the part number request process. Refer
to www.silabs.com/VCXOPartNumber to request an Si57x part number.
3 rd Option Code
Frequency Grade
H
J
K
M
N
P
Q
R
S
T
U
V
W
2.5
1.8
1.8
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
CML High
CMOS High
CML High
LVPECL Low
LVDS Low
CMOS Low
CML Low
LVPECL Low
LVDS Low
CMOS Low
CML Low
CMOS Low
CML Low
Code
A
B
C
Si570
Frequency Range Supported (MHz)
10-945, 970-1134, 1213-1417.5
10-810
10-280 (CMOS available to 160 MHz)
2 nd Option Code
Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)
A 50 61.5
B 20 31.5
C 7 20
2 nd Option Code
Note:
CMOS available to 160 MHz.
Code
Temperature Tuning Slope Minimum APR
Stability Kv (±ppm) for VDD @
± ppm (max) ppm/V (typ) 3.3 V 2.5 V
1.8 V
A 100 180 100 75 25
B         100           90            30       Note 6     Note 6
C 50 180 150 125 75
D 50 90 80 30 25
E 20 45 25 Note 6 Note 6
F 50 135 100 75 50
G 20 356 375 300 235
H         20           180           185       145        105
J 20 135 130 104 70
Si571
K 100 356 295 220 155
M 20 33 12 Note 6 Note 6
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x V DD x tuning slope.
4. Nominal Absolute Pull Range ( ± APR) = Pull range – stability – lifetime aging
= 0.5 x V DD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
Figure 6. Part Number Convention
Rev. 1.4
27
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